This invention relates to the field of heat sink and heat spreader structures and, more particularly, to heat sink/spreader structures which utilize thermoelectric effects to more efficiently dissipate thermal energy from electronic devices including Integrated Circuit (IC) devices and their associated packaging.
The performance levels of microelectronic devices (e.g., integrated circuits, power amplifiers) are continually increasing to keep pace with the demands of modern technology. Performance levels such as clock speed are closely tied to the number and density of features (e.g., transistors) patterned onto the microelectronic device. Faster processing by the microelectronic device demands faster clock speeds. Faster clock speeds, in turn, mean more switching and power dissipation per unit time.
Sub-micron transistors and other features are currently patterned onto silicon wafers with extremely high densities. For example, several million transistors can be patterned on a single square centimeter of silicon. Switching speeds as fast as a few nanoseconds can be achieved with each transistor.
In theory, the performance levels of microelectronic devices should continually improve as the size of the transistors is decreased and the density of the features is increased. In practice, however, small, closely packed features dissipate large amounts of heat which limit performance levels. Heat is often dissipated from small, select regions of the device typically by heat sinks.
Temperature control has thus emerged as the limiting factor in the design of microelectronic devices. New-age devices, such as high-power amplifiers and multi-chip modules, radiate particularly large amounts of heat. Failure to effectively conduct away heat leaves these devices at high operating temperatures, ultimately resulting in decreased performance and reliability.
Heat sinks are most efficient when there is a uniform heat flux applied over the entire base. xe2x80x9cSpreading resistancexe2x80x9d occurs when a heat sink with a large base-plate area is attached to a heat source of a smaller footprint area. This results in a higher local temperature at the location where the heat source is placed. The spreading resistance is directly influenced by the following variables:
Footprint or contact area of the heat source;
Footprint area of the heat sink base-plate;
Thickness of the heat sink base-plate;
Thermal conductivity of the heat sink base-plate;
Average heat sink thermal resistance;
Location of the heat source relative to the base-plate center point.
The typical approach to overcoming spreading resistance is to increase the size of the heat sink, increase the thickness of the base, increase the airflow across the heat sink, or decrease the incoming air temperature. These steps increase weight, noise, system complexity and expense. When a solution cannot be achieved, the impact can be lost profits due to reduced electronics"" performance, decreased reliability due to high operating temperatures, increased fan speeds and delays in new product introductions while thermal issues are resolved.
To improve the thermal performance of an electronics or integrated circuit device, heat sinks and heat spreaders are added either internally or externally to the packages. However, the typical materials utilized exhibit a variety of shortcomings including: thermal expansion mismatch between the heat spreader and the chip, excessive weight, high cost and marginal thermal performance.
U.S. Pat. No. 5,229,327, granted to Farnworth on Jul. 20, 1993 discloses structures to cool semiconductor devices with Peltier junctions. Electric current is passed through the Peltier junctions and semiconductor device (both in series) via a heat sink acting as an electrical bus and mechanical support. In addition, layers of metal and semiconductor material are progressively layered upon a semiconductor die (over a passivated layer) and junctions formed to yield peltier cooling. Power to the Peltier junctions (positive and negative terminals) is provided through the semiconductor die.
U.S. Pat. No. 5,637,921, granted to Burward-Hoy on Jun. 10, 1997 relates to a cooled electronic component package in which a single or multistage thermoelectric device contacts an integrated circuit chip via a cold plate. The chip and thermoelectric device are located within a sealed component package cavity in order to cool the chip to sub-ambient temperatures without condensation.
U.S. Pat. No. 5,714,791, granted to Chi, et al. on Feb. 3, 1998 discloses a micromachined Peltier device in which a silicon substrate is doped from one face to yield thin P and N-type thermoelements on top of a thin silicon membrane. The cold junctions of the thermoelements are located above a cavity (aperture) to minimize thermal conduction through the silicon substrate.
U.S. Pat. No. 6,196,002, granted to Newman, et al. on Mar. 6, 2001 relates to a ball grid array (BGA) integrated circuit package containing a thermoelectric device cooling the IC chip. Power for the thermoelectric cooler is supplied by the BGA package via conductive contacts. The thermoelectric cooler is positioned partially within the package substrate and one face (which contacts the IC chip) is cooler than the opposite thermoelectric face.
U.S. Pat. No. 5,569,950, granted to Lewis, et al. on Oct. 29, 1996 relates to a device to monitor and control the temperature of IC chips with a thermoelectric cooler and thermocouple sensing. A thermocouple, placed between the chip and thermoelectric cooler, provides feedback to regulate power to the cooler.
U.S. Pat. No. 5,598,031, granted to Groover, et al. on Jan. 28, 1997 discloses an IC package whereby the IC chip is mounted to a separate silicon substrate (larger in surface area than chip) in order to provide heat spreading via thermal conduction. Additionally, electrical pads and circuit traces are disposed onto the substrate surface (over an oxide layer) in order to provide electrical connection between the IC chip and package.
U.S. Pat. No. 5,837,929, granted to Adelman on Nov. 17, 1998 discloses a thermoelectric device and fabrication method in which a doped semiconducting substrate contains oppositely doped regions thereby creating positive and negative type thermoelements. These vertically oriented thermoelements are electrically isolated by etching spaces and filling the spaces with a polyimide material.
U.S. Pat. No. 4,211,888, granted to Stein, et al. on Jul. 8, 1980 relates to a thermopile in a star-like pattern on top of a semiconductor substrate. One thermoelement type is formed by doping regions on the substrate and the dissimilar thermoelement type is a metal layer deposited over an oxide. The center junctions of the thermopile are heated by a source of thermal radiation to be measured.
U.S. Pat. No. 5,956,569, granted to Shiu, et al. on Sep. 21, 1999 relates to a thermoelectric cooler structure and fabrication method in which the cooler is formed on the backside of a semiconductor substrate. The thermoelements, perpendicularly oriented to the substrate, are fabricated by etching the substrate, depositing doped polysilicon layers, oxide insulating layers and metal contact layers.
U.S. Pat. No. 4,646,126, granted to Iizuka on Feb. 24, 1987 relates to a multiple IC chips mounted to a separate silicon substrate (via an oxide layer) and wiring layers interconnecting them.
U.S. Pat. Nos. 5,777,385 and 6,162,659, granted to Wu on Jul. 7, 1998 and Dec. 19, 2000 respectively disclose an electronic package structure in which a silicon heat spreader substrate is bonded to the backside to an IC chip via discrete, raised solder joints.
U.S. Pat. No. 5,032,897, granted to Mansuria, et al. on Jul. 16, 1991 discloses an integrated circuit package in which the IC chip is bonded to a thermoelectric cooler (thermoelements oriented perpendicular to the IC chip) and positioned within the package cavity.
U.S. Pat. No. 6,222,113, granted to Ghoshal on Apr. 24, 2001 relates to a thermoelectric cooler whose thermocouples are mounted to a doped semiconducting substrate with discrete conductive regions corresponding to each electrical interconnection member connecting both thermoelement types. Power is thereby supplied to the thermoelectric cooler""s thermocouples (mounted between the two substrates) via both substrates.
U.S. Pat. No. 6,094,919, granted to Bhatia on Aug. 1, 2000 relates to an IC package whose lid contains an integrated thermoelectric cooler comprising thermoelements oriented perpendicularly to the lid and IC chip.
U.S. Pat. No. 5,061,987, granted to Hsia on Oct. 29, 1991 discloses an electronic package comprising a silicon substrate to which an IC chip is bonded. Electrical pads and circuit traces are disposed to the faces of the substrate and conductive vias are formed (through doping) to electrically connect both substrate faces. Additionally, a silicon cover is hermetically sealed to the substrate.
U.S. Pat. No. 4,092,614, granted to Sakuma, et al. on May 30, 1978 discloses a semiconductor laser in which a silicon crystal body is sandwiched between a metal body and semiconductor laser crystal body thereby providing a thermal and electrical path through the entire sandwich.
U.S. Pat. No. 6,091,142, granted to Lee on Jul. 18, 2000 relates to a stacked semiconductor package in which multiple IC chips are mounted between and supported by becker and cap structures. Additionally, one heat sink is mounted to the wire bond pads and another is mounted under each chip, thereby requiring at least one heat sink per IC chip. Both heat sinks protrude from the becker and cap to radiate heat.
U.S. Pat. No. 5,051,865, granted to Kato on Sep. 24, 1991 discloses a stacked semiconductor structure in which a plurality of chip sets (each comprised of a heat plate sandwiched by two IC chips) are bonded and electrically interconnected. Bonding between chip and heat sink is accomplished through conductive paste or solder in order for electrical power to be transferred between components.
U.S. Pat. No. 4,698,662, granted to Young, et al. on Oct. 6, 1987 relates to a multichip module is in which IC chips are dielectrically bonded to a silicon substrate which, in turn, is dielectrically bonded to a heat sink. Electrical conductive traces are deposited onto the substrate""s surface to provide electrical connection between the chips and package pins.
Now, the field of Thermoelectricity relates to the thermodynamic effects of temperature differentials, electric potential gradients and current flow in single and multiple dissimilar electrical conductors or semiconductors. There are basically three effects which comprise this field including: the Seebeck Effect, the Peltier Effect and the Thomson Effect.
In 1821, Seebeck found that when two dissimilar conducting or semiconducting materials are joined to each other at both ends and if there is a temperature differential between these two ends, an EMF, or voltage, will be established within the two materials. This effect is called the Seebeck Effect. The effect arises because the presence of a temperature gradient in a material causes a carrier-concentration gradient and an electric field is established which causes the net flow of charge carriers when the conductors are joined into a closed electrical circuit.
In 1834, Peltier observed that heat was either liberated or absorbed at the junction of two dissimilar conductors or semiconductors when an electric current was passed through the junction. Measurements established that the rate of absorption or liberation of heat at the junction was directly proportional to the electric current. The effect arises because the potential energy of the charge carriers is in general different in the two conductors and also because the scattering mechanisms that govern the equilibrium between the charge carriers and the crystal lattice differ in the two conductors. Therefore, in order to maintain a conservation of energy as well as a conservation of charge when charge carriers move across the junction, energy must be interchanged with the surroundings of the junction. As in the case of the Seebeck Effect, the Peltier Effect cannot be ascribed to either material alone but rather is a consequence of the junction.
In 1857, Thomson found that an energy interchange with the surroundings took place throughout the bulk of a conductor if an electric current was allowed to flow while a temperature gradient existed in the conductor. The rate of energy absorbed or liberated per unit length was proportional to the product of the electric current and the temperature gradient. The reasons for the existence of the Thomson Effect are essentially the same as those that cause the Peltier Effect. However, the difference in the potential energy of the charge carriers and in the scattering mechanisms are the consequences of the temperature gradient and not of the inhomogeneities in the conductor.
Additionally, charge carriers which flow (induced by a voltage) from one region of any conductive or semiconductive material to another carry with them small quantities of heat energy. If the carriers originally at one temperature in the conductor are displaced to cooler surroundings, they must discharge their excess kinetic energy by collisions with the lattice, thereby maintaining a conservation of energy. This process assists the normal thermal conduction of heat energy in the conductor, which would occur in the absence of charge carrier (electric current) flow.
By combining the electric charge induced (active) heat transfer mechanisms created by the thermoelectric effects with the thermal conduction/radiation (passive) heat transfer mechanisms of typical heat sink/heat spreader structures, a more effective heat management structure is produced.
Accordingly, it is the overall object of the present invention to develop and construct heat dissipating IC device structures which utilize thermoelectric effects in order to more effectively transfer thermal energy from electronic circuitry.
One object of the present invention is to provide a heat dissipating IC device structure in which the silicon substrate itself is part of a thermoelectric couple, which may have an external electric potential applied.
An additional object of the present invention provides a heat dissipating IC device structure comprising a thermoelectric couple with elements connected together at both ends. When subjected to a temperature gradient, an EMF and corresponding current is established within the couple resulting in the absorption and liberation of heat at these junctions without the need for external electrical power.
Another object of the present invention is to provide a heat dissipating IC device structure, comprising of simply an electrically conductive or semiconductive material, wherein the material has an external electric potential applied in order to induce multiple heat transfer effects through the structure.
Yet, another object of the present invention is to provide the thermoelectric couple or conductive material of the heat dissipating IC device structure in electrical series with an external electric load such as an electronic component or other thermoelectric device.
Again, another object of the present invention is to provide the thermoelectric couple or conductive material of the heat dissipating IC device structure as a resistive load for an electronic component or power supply circuit in order to reduce electrical power consumption of the system.
Still, another object of the present invention is to provide a heat dissipating IC device structure whereby the thermoelement couple, when subjected to a temperature gradient, provides electrical power to an external load.
A further object of the present invention is to provide unique methods of delivering electrical power to each thermoelement, conductor or substrate.
Another object of the present invention is to provide a heat dissipating IC device structure comprised of multiple thermoelectric couples, in a planar configuration.
Yet another object of the present invention is to have a cascaded, or multistage xe2x80x9cplanarxe2x80x9d thermoelectric device structure wherein each successive stage is added to the horizontal plane.
A further object of the present invention includes a single or multistage heat sink/spreader, each stage consisting of at least one thermoelement couple, in which all thermoelements are formed within the IC device substrate through selecting doping techniques. Various electrical isolation techniques are additionally disclosed.
An additional object is to reduce the coefficient of thermal expansion mismatch between integrated heat spreaders and IC device structures.
Lastly, it is an object of the present invention is to combine all of these unique design aspects and individual fabrication techniques into effective and manufacturable heat dissipating IC device structures.